Field effect transistor and method for fabricating it

ABSTRACT

The invention relates to a field effect transistor in which the planar channel region on the upper surface of the elevation is extended in width by means of additional vertical channel regions on the lateral surfaces of the elevation. Said additional vertical channel regions connect directly to the planar channel region (vertical extended channel regions). Said field effect transistor has the advantage that a significant increase in the effective channel width for the current flow I ON  can be guaranteed relative to conventional transistor structures used up until the present, without having to accept a reduction in the achievable integration density. Said field effect transistor furthermore has a low reverse current I OFF . The above advantages are achieved without the thickness of the gate insulators up to the region of the charge transfer tunnels having to be reduced or a reduced stability.

CLAIM FOR PRIORITY

This application is a national stage of PCT/EP02/07028, filed in theGerman language on Jun. 25, 2002, and which claims the benefit ofpriority to German Application No. DE 101 31276.8, filed in the Germanlanguage on Jun. 28, 2001.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a field-effect transistor and a methodfor fabricating it.

BACKGROUND OF THE INVENTION

The characteristic parameters of conventional field-effect transistors,in particular of planar MIS field-effect transistors (MISFET), areincreasingly impaired with continual structural miniaturization(scaling) and increasing of the packing density of integrated circuits.Thus, by way of example, with a shortened channel length of thetransistor the threshold voltage V_(T) of the transistor decreases. Atthe same time, with a shortened channel length, the field strength inthe channel region and the reverse current I_(OFF) increase (SCE: shortchannel effect; roll-off). Furthermore, with a reduced channel width,the forward current I_(ON) varies in a non-linear manner. In addition,the geometry and doping of the field-effect transistor are modified atthe junction between the channel and the insulation. Generally, in theevent of scaling, the channel boundaries gain in relative importancewith respect to the central channel region (NCE: narrow channel effect,INCE: inverse narrow channel effect).

In order, despite the difficulties mentioned, to be able to ensure animprovement/maintenance of the performance of field-effect transistorsin the context of advancing structural miniaturization (scaling), aseries of measures are proposed or implemented. Thus, by way of example,a matched scaling of the internal operating voltage levels is effectedat the same time as the MISFET scaling. Furthermore, the doping profilesof the well and channel regions and also of the source and drain regionsare generally optimized. At the same time, scaling of the gate insulatorwith regard to thickness and material is usually carried out.

Further improvements result from the use of salicided source and drainregions (S/D) and salicided gate electrodes. A further improvement canbe obtained by minimization of the parasitic resistances or capacitancesof the connection metallization, for example through the use of copperwiring, and of the intermediate insulators, for example through the useof so-called “low-k” materials. In the case of DRAM memory cells, it isalso possible to adapt the read-out logic to the “ON”, currents—whichdecrease with each “shrink”—of the respective array transistors (e.g.reduction of the resistances of the gate tracks).

A further possibility for maintaining or improving the performance offield-effect transistors consists in the use of modified transistorarrangements which, for example, have elevated source/drain regions(“elevated S/D”) or which are based on a so-called “silicon oninsulator” technology (SOI) or which have a material with a highercarrier mobility, e.g. SiGe, in the channel region. Additionalpossibilities which result when the operating temperature is lowered arenot presented here.

The introduction of the trench field isolation (STI: shallow trenchisolation) instead of conventional LOCOS field isolation likewisecontributes to improving the situation. If a trench field isolation(STI: shallow trench isolation) is used instead of a conventional LOCOSfield isolation, then it is generally necessary to take additionalmeasures to minimize the so-called “inverse narrow channel effect”(INCE). Thus, by way of example, a positive step height of the STI upperedge above the semiconductor surface is set in order to avoid aso-called “wraparound gate”. Furthermore, a local doping of thetransistor channel at the junction with the field isolation, theso-called “corner region”, may be provided in addition to the normalchannel doping.

Oxidation of the STI sidewalls during the STI processing may result inthe production of a so-called “bird's beak geometry” and edge roundingof the active regions at the junction with the trench isolation. In theprocess sequence, the terms mentioned here are “corner rounding”, “miniLOCOS” or “post CMP oxidation”. These measures also serve to counteractthe “inverse narrow channel effect” (INCE). This effect can bereinforced by prior lateral etching-back of the pad oxide. Edge roundingof the active regions can also be produced by means of thermal surfacetransformation. Furthermore a nitride spacer guard ring may be provided.In order to avoid a gate overlap over the corner region, it is possibleto provide a self-aligned termination of the gate edge before the fieldisolation boundary. This may be done for example by joint patterning ofpoly-gate and active region during the STI patterning.

Despite all these measures, however, it is becoming more and moredifficult to ensure adequate forward currents ION above a feature sizeof about 100 nm, without the risk of tunneling or degradation of thegate oxide stability of the MISFET. Therefore, a series of alternativetransistor arrangements have been proposed.

The document U.S. Pat. No. 4,979,014 discloses a MOS transistor having aweb-type elevation on a semiconductor substrate. The channel of thistransistor is arranged along the web-type elevation and has, besides thechannel region at the top side of the web-type elevation, two furtherchannel regions at the side walls of the web-type elevation. Thetransistor in accordance with document U.S. Pat. No. 4,979,014 exhibitsa pronounced “corner effect”, which is used to produce a large depletionzone.

The document Huang et al. “Sub 50 nm FinFET; PMOS” IEDM 1999 discloses atransistor called “FinFET”, which has a dual gate structure at the sidewalls of the web-type elevation (“Fin”). The FinFET avoids the INCE bymeans of a thicker insulator layer on the narrow Fin covering surface.

Unfortunately, all of the measures mentioned either have only limitedefficacy or they require a high process engineering outlay.

SUMMARY OF THE INVENTION

The present invention provides a field-effect transistor and a methodfor fabricating it which reduce or avoid the abovementioneddifficulties. In particular, the present invention provides afield-effect transistor makes available an adequate forward current IONand which can be fabricated with a low outlay, compatibly with theprevious conventional integration process for planar MOSFETs.

One embodiment of the present invention provides a field-effecttransistor which comprises of the following features:

-   -   a) at least one web-type elevation, which is arranged on a        semiconductor substrate and has an upper surface and lateral        surfaces,    -   b) a first gate oxide layer, which is arranged on the upper        surface of the web-type elevation,    -   c) a first gate electrode, which is arranged on the first gate        oxide layer, the first gate electrode having an upper surface        and lateral surfaces,    -   d) a second gate oxide layer, which is arranged at least on a        part of the lateral surfaces of the web-type elevation and the        first gate electrode,    -   e) a second gate electrode, which is arranged on the second gate        oxide layer and the upper surface of the first gate electrode        and    -   f) source and drain regions, which are arranged on the        elevation.

A further emboidment of the present invention provides a field-effecttransistor comprising the following features:

-   -   a) at least one web-type elevation, which is arranged on a        semiconductor substrate and has an upper surface and lateral        surfaces,    -   b) a first gate oxide layer, which is arranged at least on a        part of the lateral surfaces of the web-type elevation,    -   c) a first gate electrode, which is arranged on the first gate        oxide layer, the first gate electrode layer having an upper        surface and lateral surfaces,    -   d) a second gate oxide layer, which is arranged on the upper        surface of the web-type elevation and the upper surface of the        first gate electrode,    -   e) a second gate electrode, which is arranged on the second gate        oxide layer and the lateral surfaces of the first gate        electrode, and    -   f) source and drain regions, which are arranged on the        elevation.

Further, another embodiment of the invention provides a method forfabricating a field-effect transistor, which comprises the followingsteps:

-   -   a) a semiconductor substrate with a first gate oxide layer        applied thereon and a first gate electrode layer applied to the        gate oxide layer is provided,    -   b) at least one web-type elevation with an upper surface and        lateral surfaces is produced, the first gate oxide layer and the        first gate electrode layer being arranged on the upper surface,    -   c) a second gate oxide layer is produced at least on a part of        the lateral surfaces of the web-type elevation and the first        gate electrode layer,    -   d) a second gate electrode layer is applied, so that the second        gate electrode layer is arranged on the second gate oxide layer        and the upper surface of the first gate electrode layer, and    -   e) the first and second gate electrode layers are patterned to        form first and second gate electrodes and source and drain        regions are produced.

The field-effect transistor according to the invention has the advantagethat a significant increase in the effective channel width for theforward current ION can be ensured compared with previously known,conventional transistor structures, without having to accept a reductionof the integration density that can be attained. In the case of thefield-effect transistor according to the invention, the planar channelregion at the upper surface of the elevation is extended in width byadditional vertical channel regions at the side areas of the elevation.These additional vertical channel regions directly adjoin the planarchannel region (vertical extended channel regions). Furthermore, thefield-effect transistor according to the invention has a small reversecurrent I_(OFF). These advantages are obtained without having to reducethe thickness of the gate insulator into the region of the tunneling ofcharge carriers or reduced stability.

In this case, the additional vertical channel regions are obtainedaccording to the invention by utilizing the vertical semiconductorsurfaces which can preferably be produced analogously to theconventional planar transistor arrangement during the STI patterning(“shallow trench isolation”) and form the vertical STI sidewalls. Theprocess for fabricating the transistor according to the invention isthus so closely related to the process sequence of the conventionalSTI-isolated, planar transistor that conventional, planar transistorscan be integrated and combined very simply on the same chip withtransistors according to the invention.

Between the planar channel region and the vertical channel regions thereexists a transition region in the form of a convexly curved edge,arranged in the source/drain direction, on the web-type elevation asconstituent part of the active channel. In the case of previouslyproposed transistor arrangements, this edge always led to a pronounced“corner effect” which adversely influenced the threshold voltage of thetransistor. In the case of the field-effect transistor according to theinvention, this problem is largely avoided by the special enclosurearrangement which has the first and second gate oxide layers and alsothe first and second gate electrodes.

In accordance with one preferred embodiment of the field-effecttransistor according to the invention, the second gate oxide layer ismade thicker on the lateral surfaces of the first gate electrode than onthe lateral surfaces of the web-type elevation. Furthermore, it ispreferred if an insulating spacer is arranged on the second gate oxidelayer at the level of the first gate electrode. This makes it possibleto further reduce the electric field strength at the edges.

In accordance with a further preferred embodiment of the field-effecttransistor according to the invention, the edges of the web-typeelevation are rounded between the upper surface and the lateralsurfaces. This rounding can preferably be produced with the aid of ashort high-temperature process. Accordingly, the transistor according tothe invention can be processed with a significantly reduced temperaturebudget. This yields advantages interalia in respect of doping profilesand performance. Moreover, as a result, the transition region betweenthe planar and vertical channel regions is kept small, and virtually theentire width and depth of the geometrical channel area can be utilizedas active channel even in the event of a very highly scaled transistorgeometry.

In this case, it is particularly preferred if the radius of curvature ofthe edges is of the order of magnitude of the layer thickness of thefirst or second gate oxide layer. Accordingly, the threshold voltage ofthe so-called “parasitic corner device” can be brought to a value whichis greater than the value of the threshold voltage of the planar channelregion. The resulting electric field strength along the surface of theedge curvature consequently does not exceed the electric field strengthprevailing in the planar part of the channel.

In accordance with a further preferred embodiment of the field-effecttransistor according to the invention, spacers are arranged between thesource region and the gate electrodes and also between the drain regionand the gate electrodes. Furthermore, it is preferred if the first gateelectrode has a polysilicon layer. Moreover, it is particularlypreferred if the second gate electrode has a polysilicon-metal doublelayer or a polycide layer. In accordance with a further preferredembodiment of the field-effect transistor according to the invention,the part of the lateral surfaces of the web-type elevation which iscovered by a gate oxide layer is bounded by a trench isolation.Furthermore, it is particularly preferred if the doping profile depth ofthe source and drain regions is greater than the extent of the part ofthe lateral surfaces of the web-type elevation which is covered by agate oxide layer.

In accordance with one preferred embodiment of the fabrication methodaccording to the invention, the web-type elevation is produced with thepatterning of the trenches for a trench isolation. In this case, it isparticularly preferred if the trenches for the trench isolation arefilled with oxide and etching-back, preferably after a CMP step, iscarried out, so that a part of the lateral surfaces of the web-typeelevation is uncovered.

In accordance with a further preferred embodiment of the fabricationmethod according to the invention, at least one thermal process iscarried out for rounding the edges of the web-type elevation between theupper surface and the lateral surfaces. Furthermore, it is particularlypreferred if the gate oxide layers are in each case produced by thermaloxidation.

In accordance with a further preferred embodiment of the fabricationmethod according to the invention, the second gate oxide layer isproduced by selective oxidation, so that the second gate oxide layer ismade thicker on the lateral surfaces of the first gate electrode than onthe lateral surfaces of the web-type elevation. Furthermore, it ispreferred if an insulating spacer is produced after the production ofthe first gate electrode layer, so that an insulating spacer is arrangedon the second gate oxide layer at the level of the first gate electrode.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in more detail below with reference tofigures of the drawings, in which:

FIGS. 1 and 2 show a first embodiment of the field-effect transistoraccording to the invention.

FIGS. 3 a–3 h show a first embodiment of the method according to theinvention for fabricating a field-effect transistor.

FIG. 4 shows a further embodiment of the field-effect transistoraccording to the invention.

FIG. 5 shows a further embodiment of the field-effect transistoraccording to the invention.

FIG. 6 shows a further embodiment of the field-effect transistoraccording to the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2 show a first embodiment of the field-effect transistoraccording to the invention. In this case, FIG. 1 shows the generalstructure of this embodiment of the field-effect transistor according tothe invention, while FIG. 2 illustrates the details of this according beseen according which is embodiment of the field-effect transistor to theinvention in a cross section. As can from FIG. 1, the field-effecttransistor to the invention has a web-type elevation 2, arranged on asemiconductor substrate 1 and has an upper surface 2 a and two lateralsurfaces 2 b. The web-type elevation 2 constitutes the activesemiconductor region in this case.

The active semiconductor region 2 with vertical connection to thesemiconductor substrate 1 is laterally insulated from adjacent activeregions (not illustrated) by STI field isolation regions 3. The surface2 a, 2 b of the active region is patterned into source and drain regionsand also into a planar channel region. The web-type elevation 2 projectsabove the STI surface, as a result of which the side areas 2 b of theactive region are in part not covered by the isolation 3. Theseuncovered side areas, directly adjoining the corresponding planarregions, are patterned identically into source, drain and channelregions. In this case, the height difference between the activesemiconductor region and the STI surface corresponds to the width of thevertical channel regions. The doping profile depth of the source anddrain regions is preferably greater than the said height difference.

As can be seen from FIG. 2, the field-effect transistor according to theinvention has a first gate oxide layer 4, which is arranged on the uppersurface 2 a of the web-type elevation 2. Furthermore, a first gateelectrode 5 is provided, which is arranged on the first gate oxide layer4, the first gate electrode having an upper surface and two lateralsurfaces. A second gate oxide layer 6 is arranged on the lateralsurfaces 2 b of the web-type elevation 2 and the first gate electrode 4.Furthermore, a second gate electrode 7 is arranged on said second gateoxide layer 6 and on the upper surface of the first gate electrode 5.

The relief structure comprising active and sunk STI surface is thuscovered by a double gate electrode in the channel region. In this case,the first gate electrode 5 is preferably composed of highly dopedpolysilicon, while the second gate electrode 7 preferably has apolysilicon-metal layer stack. In this case, the two gate electrodes 5,7 are arranged such that the first gate electrode 5 covers exclusivelythe planar part of the active region and approximately terminates withthe sidewalls thereof, while the second gate electrode 7 covers thevertical side walls of the active region and encloses the first gateelectrode 5.

In this case, the second gate electrode 7 makes contact with the firstgate electrode 5 on the planar surface thereof, while it is insulatedfrom the lateral sidewalls thereof by the second gate oxide layer 6.

In the case of the present embodiment of the field-effect transistoraccording to the invention, the edge 8 of the active region is rounded.The radius of curvature of this rounding is of the order of magnitude ofthe gate oxide thickness. Furthermore, the channel region is flanked onthe source and drain side by spacers (not shown) which laterallyinsulate the dual gate electrode 5, 7 from the S/D contact areas.

FIGS. 3 a–3 h show a first embodiment of the method according to theinvention for fabricating a field-effect transistor. After a fewpreparatory fabrication steps, a first gate oxide layer 4 and also afirst gate electrode layer 5 and pad nitride layer 10 are produced on asemiconductor substrate 1, in particular a silicon substrate. In thiscase, the gate oxidation can be carried out for example with the aid ofa thermal oxidation. The gate electrode layer and pad nitride depositionis effected for example with the aid of CVD methods. The resultantsituation is shown in FIG. 3 a.

Afterward, using a resist mask 11, this layer stack is patternedtogether with the STI patterning. This joint patterning is effected forexample with the aid of chemical-physical dry etching. Consequently, aweb-type elevation 2 with an upper surface 2 a and two lateral surfaces2 b is produced, the first gate oxide layer 4 and the first gateelectrode layer 5 being arranged on the upper surface 2 a. The edges 8between the upper surface 2 a and the two lateral surfaces 2 b are cutsharply, virtually at 90° C., in this processing stage. The resultantsituation is shown in FIG. 3 b.

The following are then effected: the removal of the resist mask 11 andalso cleaning and a brief thermal oxidation in order to improve thequality of the perpendicular side areas, and also sealing of thesidewalls of the first gate electrode layer 5. The surface reliefproduced is then filled with oxide 3 (FIG. 3 c), thermally densified andplanarized to a nitride residual thickness by means of a CMP method(chemical mechanical polishing) (FIG. 3 d). The thermal processes ofthis processing section result in slight widening of the first gateoxide layer 4 at the edge 8 and rounding of the edges 8 between theupper surface 2 a and the two lateral surfaces 2 b of the web-typeelevation 2.

The STI oxide 3 is subsequently etched back in a planar manner down to adefined depth by means of anisotropic etching using a block mask 12,which covers all the regions for transistors without intended verticalchannel extension. This etching has a certain selectivity with respectto the pad nitride layer 10, so that the upper surfaces 2 a of theweb-type elevations 2 still remain reliably covered with silicon nitride10. The remaining STI filling depth is dimensioned so as to guarantee alater reliable field isolation. The resultant situation is shown in FIG.3 e.

After the removal of the block mask, cleaning/overetching, the 2^(nd)gate oxidation is effected (FIG. 3 f). In this case, the second gateoxide layer 6 grows on the uncovered sidewalls of the web-type elevation2 and on the uncovered sidewalls of the first gate electrode layer 5.This oxidation step additionally widens the first gate oxide layer 4 atthe edges 8 and further reduces the curvature of the substrate and polyedges. Afterward, the pad nitride residual layer 10 that remained on thesurfaces of the first gate electrode layer is removed (FIG. 3 g) and,after further cleaning, the second gate electrode layer 7 is deposited(FIG. 3 h).

Afterward, using a mask (not shown), the first and second gate electrodelayers are jointly patterned with the aid of etching, preferably plasmaetching, the etching stopping in the first gate oxide layer. This isthen followed by the further processing including fabrication of thesource/drain regions through to the complete circuit in accordance withthe conventional process sequence.

FIG. 4 shows a further embodiment of the field-effect transistoraccording to the invention. As can be seen from FIG. 4, the furtherembodiment of the field-effect transistor according to the inventionalso has a web-type elevation 2, which is arranged on a semiconductorsubstrate 1 and has an upper surface 2 a and two lateral surfaces 2 b.The web-type elevation 2 constitutes the active semiconductor region inthis case.

The active semiconductor region with vertical connection to thesemiconductor substrate is again laterally insulated from adjacentactive regions by STI field isolation region 3. The surface of theactive region is patterned into source and drain regions and planarchannel regions. It projects above the STI surface, as a result of whichthe sidewalls of the active region are in part uncovered. Theseuncovered side walls, directly adjoining the corresponding planarregions, are patterned identically into source, drain and channelregions. The height difference between active and STI surfacecorresponds to the width of the vertical channel regions. The dopingprofile depth of the source and drain regions is preferably greater thansaid height difference.

The relief structure comprising active and sunk STI surface is thuscovered by a dual gate electrode 5, 7 in the channel region. In thiscase, the first gate electrode 5 is preferably composed of highly dopedpolysilicon, while the second gate oxide 7 preferably has apolysilicon-metal layer stack. The two gate electrodes 5, 7 are arrangedin such a way that the first gate electrode 5 covers exclusively thevertical part 2 b of the active region 2 and terminates approximatelywith the upper surfaces thereof, while the second gate electrode 7covers the upper surface of the active region 2 and encloses the firstgate electrode 5. In this case, the second gate electrode makes contactwith the first gate electrode on the lateral surfaces thereof, while itis insulated from the upper sidewalls thereof by the second gate oxidelayer 6. The channel region is covered by the second gate oxide layer 6on its planar part and by the first gate oxide layer 4 on its verticalareas.

FIG. 5 shows a further embodiment of the field-effect transistoraccording to the invention. The embodiment of the field-effecttransistor according to the invention as shown in FIG. 5 essentiallycorresponds to the embodiment of the field-effect transistor accordingto the invention as shown in FIG. 2, with the exception that the secondgate oxide layer 6 is made thicker on the lateral surfaces of the firstgate electrode 5 than on the lateral surfaces 2 b of the web-typeelevation 2. The thickening of the second gate oxide layer 6 on thelateral surfaces of the first gate electrode 5 is achieved by aselective gate oxidation, exploiting the fact that, given suitablyselected process parameters, a higher oxidation rate is obtained onpolysilicon than on monocrystalline silicon.

FIG. 6 shows a further embodiment of the field-effect transistoraccording to the invention. The embodiment of the field-effecttransistor according to the invention as shown in FIG. 6 essentiallycorresponds to the embodiment of the field-effect transistor accordingto the invention as shown in FIG. 2, with the exception that a spacer14, in particular an oxide spacer, is arranged on the second gate oxidelayer 6 at the level of the first gate electrode 5. In this case, thespacer 14 can be formed on the sidewalls of the first gate electrodelayer 5 immediately after the patterning thereof, still before theformation of the web-type elevation 2. The oxidation for producing thesecond gate oxide layer 6 then reinforces this spacer 14 by anadditional oxide layer directly on the lateral surfaces of the firstgate electrode layer 5.

The field-effect transistor according to the invention has the advantagethat a significant increase in the effective channel width for theforward current ION can be ensured compared with previously known,conventional transistor structures, without having to accept a reductionof the integration density that can be attained. In the case of thefield-effect transistor according to the invention, the planar channelregion at the upper surface of the elevation is extended in width byadditional vertical channel regions at the side areas of the elevation.These additional vertical channel regions directly adjoin the planarchannel region (vertical extended channel regions).

Furthermore, the field-effect transistor according to the invention hasa small reverse current I_(OFF). These advantages are obtained withouthaving to reduce the thickness of the gate insulator into the region ofthe tunneling of charge carriers or reduced stability.

1. A field-effect transistor, comprising: at least one web-typeelevation, which is arranged on a semiconductor substrate and has anupper surface and lateral surfaces; a first gate oxide layer, which isarranged on the upper surface of the web-type elevation; a first gateelectrode, which is arranged on the first gate oxide layer, the firstgate electrode having an upper surface and lateral surfaces; a secondgate oxide layer, which is arranged at least on a part of the lateralsurfaces of the web-type elevation and the first gate electrode; asecond gate electrode, which is arranged on the second gate oxide layerand the upper surface of the first gate electrodes; and source and drainregions, which are arranged on the web-type elevation.
 2. Thefield-effect transistor as claimed in claim 1, wherein the second gateoxide layer is made thicker on the lateral surfaces of the first gateelectrode than on the lateral surfaces of the web-type elevation.
 3. Thefield-effect transistor as claimed in claim 1, wherein an insulatingspacer is arranged on the second gate oxide layer at the level of thefirst gate electrode.
 4. The field-effect transistor as claimed in claim1, wherein 20 spacers are arranged between the source region and thegate electrodes and also between the drain region and the gateelectrodes.
 5. The field-effect transistor as claimed in claim 1,wherein the first gate electrodes has a polysilicon layer.
 6. Thefield-effect transistor as claimed in claim 1, wherein the second gateelectrode has a polysilicon-metal double layer or a polycide layer. 7.The field-effect transistor as claimed in claim 1, wherein the part ofthe lateral surfaces of the web-type elevation which is covered by agate oxide layer is bounded by a trench isolation.
 8. The field-effecttransistor as claimed in claim 1, wherein the doping profile depth ofthe source and drain regions is greater than the extent of the part ofthe lateral surface of the web-type elevation which is covered by a gateoxide layer.
 9. A field-effect transistor, comprising: at least oneweb-type elevation, which is arranged on a semiconductor substrate andhas an upper surface and lateral surfaces; a first gate oxide layer,which is arranged at least on a part of the lateral surfaces of theweb-type elevation; a first gate electrodes, which is arranged on thefirst gate oxide layer, the first gate electrode having an upper surfaceand lateral surfaces; a second gate oxide layer, which is arranged onthe upper surface of the web-type elevation and the upper surface of thefirst gate electrode; a second gate electrode, which is arranged on thesecond gate oxide layer and the lateral surfaces of the first gateelectrodes; and source and drain regions, which are arranged on theweb-type elevations.
 10. The field-effect transistor as claimed in claim1, wherein the edges of the web-type elevation are rounded between theupper surface and the lateral surfaces.
 11. The field-effect transistoras claimed in claim 10, wherein the radius of curvature of the edges isof the order of magnitude of the layer thickness of the first or secondgate oxide layer.
 12. A method for fabricating a field-effecttransistor, comprising: providing a semiconductor substrate with a firstgate oxide layer applied thereon and a first gate electrode layerapplied to the gate oxide layer; producing at least one web-typeelevations with an upper surface and lateral surfaces, the first gateoxide layer and the first gate electrode layer being arranged on theupper surface; producing a second gate oxide layer at least on a part ofthe lateral surfaces of the web-type elevations and the first gateelectrode layer; applying a second gate electrode layer is applied, sothat the second gate electrode layer is arranged on the second gateoxide layer and the upper surface of the first gate electrode layer; andpatterning the first and second gate electrode layers to form first andsecond gate electrodes and source and drain regions are produced. 13.The method as claimed in claim 12, wherein the web-type elevation isproduced with the patterning of the trenches for a trench isolation. 14.The method as claimed in claim 13, wherein the trenches for the trenchisolation are filled with oxide and etching-back is carried out, so thata part of the lateral surfaces of the web-type elevations is uncovered.15. The method as claimed in claim 14, wherein a CMP step is carried outprior to the etching-back.
 16. The method as claimed in claim 12,wherein at least one thermal process is carried out for rounding theedges of the web-type elevation between the upper surface and thelateral surfaces.
 17. The method as claimed in claim 12, wherein thegate oxide layers are in each case produced by a thermal oxidation. 18.The method as claimed in claim 12, wherein the second gate oxide layeris produced by selective oxidation, so that the second gate oxide layeris made thicker on the lateral surfaces of the first gate electrode thanon the lateral surfaces of the web-type elevation.
 19. The method asclaimed in claim 12, wherein an insulating spacer is produced after theproduction of the first gate electrode layer, so that an insulatingspacer is arranged on the second gate oxide layer at the level of thefirst gate electrode.